1. Field
Various features relate to a programmable built-in-self-tester in a memory controller.
2. Background
A package with a built-in-self tester (BIST) is a package that is capable of testing itself. That is, the package can perform self-diagnosis tests to check the operation and/or functionality of the package. FIG. 1 illustrates a conventional memory package 100 with a built-in-self tester. For purposes of clarity, not all components are shown. As shown in FIG. 1, the memory package 100 includes a memory 102, a memory controller 104, a built-in-self tester (BIST) 106 and a system bus 108. The memory controller 104 is coupled to the memory 102. The memory controller 104 controls the read and write operations of the memory 102. The BIST 106 is coupled to the memory controller 104 through the system bus 108. In order for the BIST 106 to perform testing operations on the memory 102, the BIST 106 must communicate with and send the instructions to the memory controller 104 through the system bus 108. These instructions are then sent by the memory controller 104 to the memory 102. Any data from the memory 102 is received by the memory controller 104, which then provides the data to the BIST 106 through the system bus 108.
There are several disadvantages to this conventional memory BIST configuration. First, this configuration makes it impossible to know the cause of any failure in the test performed by the BIST 106. That is, in this configuration, the BIST 106 is unable to determine whether the failure of the test is because of the memory 102 or the memory controller 104. This is the case because the BIST 106 is communicating with the memory controller 104 and not directly with the memory 102. Thus, the memory 102 could be working properly, but there could be failures with the memory controller 104.
Second, this configuration is limited by the capabilities of the memory controller 104. Since the memory controller 104 acts as an intermediate between the BIST 106 and the memory 102, any operation performed on the memory 102 is limited by the capabilities of the memory controller 104, even if the BIST 106 is capable of performing other operations and/or functionalities. For instances, if the memory controller 104 is capable of performing only one type of scan (e.g., scan A) and the BIST 106 is capable of performing a variety of scans (e.g., scan A, scan B, etc. . . . ), the only scan that can be performed by the BIST 106 on the memory 102 is the one that the memory controller 104 can perform (e.g., scan A).
Third, this configuration is also limited by the capabilities of the system bus 108. The system bus 108 operates on a set of different protocols than the protocols of the memory controller 104. These differences can cause inefficiencies in the testing process.
Therefore, there is a need for an improved memory BIST that is capable of testing memory without being restricted by the limitations of a memory controller and, or system bus. Ideally, the memory BIST is programmable to perform a variety of tests.